The current state of the art of semiconductor development is the mass production of large integrated circuits “IC's” containing several million active components. One type of device fitting this description is a large Field Programmable Gate Array “FPGA.” FPGAs and other devices may operate at speeds of several hundred Megahertz and it is not unusual that these integrated circuits include over a thousand pins that bring high speed signals into and out of the integrated circuit die. With a large number of active internal components switching at high speeds, these devices consume large amounts of power. Therefore it is necessary to have a packaging solution that allows for the distribution of over a thousand high speed signal lines and also provides for a plurality of connections to supply power to the device. To solve this problem for a single FPGA, IC designers have used a technique wherein thousands of “bumps” are distributed over the surface of the FPGA via thick metal lines. It would not be unusual to have two-thousand bumps for power and another two thousand for ground. The large number of bumps reserved for power ensures only a minimal resistive drop from the surface of the device to the active devices within the FPGA.
The power and signal connections extend from the bumps present on the surface of the FPGA to balls of a ball-grid-array “BGA” package. A BGA utilized for packaging a large FPGA has approximately fifteen-hundred balls; one-thousand for input and output “I/O” connections and five-hundred for power and ground connections. Power is supplied to the balls of the BGA package through thick metal conductors to the bumps present on the surface of the FPGA.
The bumped FPGA construction and BGA package is adequate to power and connect a single FPGA but it is not adequate to power and connect a system of many FPGAs. The problems associated with the large number of signals and the high power requirements of a single FPGA are multiplied when several devices are required for use within a single system. In this case, many thick conductors are needed for power connections while many minimum width conductors are required for routing high speed input and output signals. Thus a larger substrate is needed for the increased routing requirements while, the area needed for routing all of these signals should be minimized for the highest possible system performance.
Improved performance is obtained with the utilization of a silicon wafer as a semiconductor substrate. Even with the use of a silicon substrate, however, multiple layers with multiple cross-overs are used to route the large number of signals and power. The addition of multiple layers to allow for the requisite signal density further decreases performance and increases fabrication costs.
U.S. Pat. No. 6,221,769 discusses a method to decrease the density of signal lines and increase performance by creating a semiconductor chip package having a silicon substrate with substrate vias for connecting to a power source and other electronic devices. As shown in FIG. 1 (Prior Art), a plurality of integrated circuit dice 100 are connected to multilevel wiring layer 107 using die bonding bumps 109. Power is routed from integrated circuit die 100 through die bonding bumps 109 through the multilevel wiring layer 107 and to the bonding balls 103 via through substrate vias 105.
U.S. Pat. No. 5,236,118 describes a process for aligning and bonding of complimentary electrical structures and is hereby incorporated by reference. The described process is applicable to fabrication of semiconductor devices from separate structures and employs direct silicon bonding.
FIG. 2 (Prior Art) shows a similar structure except power is routed from the integrated circuit die 100 to contacts 110 using through-substrate vias 105. Contacts 110 can be a grid array made of ceramic or a copper based material. The prior art describes a method for drilling three thousand to five thousand substrate vias through the wafer, the substrate vias having a one millimeter diameter with one millimeter spacing. Once the substrate vias have been created in the prior art process, the vias are electroplated and standard dual damascene processing forms the multilevel wiring that connects to the substrate vias.
If standard spin-on resist processing, used to create the multilevel wiring structures, is performed with unfilled through substrate vias present in the wafer, uneven thicknesses of photoresist during spin-on of the photoresist material will occur over the surface of the wafer. Etching of the photoresist will not be uniform resulting in a large number of defects and increased fabrication cost or reduced wafer yield. This method is not suitable for mass manufacturing.
Dry film resist processing for the multilevel wiring will not have the uneven thickness issues present with wet or liquid resist processing and can be used to create thick conductors used for power routing. However, dry film processing is not suitable for feature sizes of less than twenty or thirty microns and thus dry film processing is not suitable for creation of conductors required for routing thousands of signal lines.
U.S. Pat. No. 6,379,982 discusses a semiconductor wafer-on-wafer package which is shown in FIG. 3 (Prior Art). FIG. 3 displays a cross-sectional drawing of a portion of an unsingulated die of a wafer-on-wafer package, the wafer-on-wafer package constructed for the purpose of testing and burning-in the die prior to singulation. In FIG. 3, die bond pad 202 is shown protruding slightly from the surface of device wafer 200 which is the active surface of a semiconductor die contained therein. Conductive trace 215, which may be copper, a copper based alloy, or any suitable electrically conductive material is disposed on support wafer 225 and is shown contacting bond pad connection point 204. The bond pad connection point is a solder ball or bump and is disposed upon conductive trace 215. Through-wafer via 210 is preformed in support wafer 225 prior to attaching device wafer 200 to support wafer 225. The through-wafer via is created by laser drilling, electrochemical anodization, or by an etching process and has an internal diameter of approximately sixty microns. Conductive filling material 206 is disposed within through-wafer via 210 such that an electrical connection is made to device wafer 200 via die bond 202, by bond pad connection point 204, conductive filling material 206 and bump 207. Bump 207 is electrically conductive and is used to make electrical contact to mounting pad 208 of mounting substrate 206. Gap 201 is shown between the device wafer 200 and passivation layer 205. While the prior art drawing in FIG. 3 illustrates a method of producing a silicon package with through-wafer vias, the silicon packages described do not provide connections to multiple semiconductor integrated circuits disposed on device wafer 200. Thus the wafer-on-wafer package does not appear to have multiple conductive layers of varying thicknesses necessary both to provide power and to route thousands of connections from one semiconductor IC to another.
A method of making a semiconductor package is therefore desired which supports; 1) construction of thin, fine-pitch conductors for routing signal connections between a plurality of semiconductor ICs, 2) construction of thick conductors, characterized as having large feature sizes, for the lateral conduction of power to the semiconductor ICs and 3) through-holes for conducting the power supply through a semiconductor body to facilitate the increased density of thin conductors between semiconductor ICs on the silicon substrate.